Keyword: FPGA
Space
The CCSDS 131.2-B Receiver IP Core is a complete solution to implement the core functions of a receiver compliant with the CCSDS 131.2-B standard: this standard has been conceived for Low…
Artificial Intelligence,
Space
GPU@SAT is a complete HW/SW ecosystem for space systems dedicated to Artificial Intelligence and Computer Vision applications. GPU@SAT comprises both a GPU IP Core for FPGA/ASIC enabling on-board advanced data processing and…
Artificial Intelligence,
Space
Next week our space crew will be at Space Tech Expo USA, taking place on May 2-4 2023 at Long Beach, CA. Join us and thousands of other space manufacturing and technology…
Artificial Intelligence,
Space
Between the 14th and 16th of March we will be at the 5th edition of SEFUW, the SpacE FPGA Users Workshop, at ESA-ESTEC premises in Noordwijk, The Netherlands. Looking forward to…
Cyber Security
The ECC Accelerator Suite is our IP Core dedicated to accelerate asymmetric-key cryptographic schemes based on Elliptic-Curve Cryptography (ECC) and ECC arithmetic operations. The ECC Accelerator Suite is…
Cyber Security
The RNG IP Core is a module able to generate random numbers, a primitive function widely used in encryption and cybersecurity applications. Usually random numbers are employed…
Cyber Security
The Secure Hash Algorithm (SHA) is a family of cryptographic hash functions developed and distributed by NIST. Our SHA Engine is composed of 2 independent cores. The…
Cyber Security
The Crypto-AES IP Core performs hardware acceleration of symmetric-key algorithms based on the Advanced Encryption Standard (AES) cipher, providing security functionalities for data confidentiality, integrity and authenticity.
Space
“IP Core for medium data rate PDT” is an European Space Agency project for the implementation of a flexible modulation and coding IP Core for Payload Data Transmission (PDT). IngeniArs…