The SpaceWire CODEC IP Core is a very compact macrocell providing a complete and configurable interfacing solution for high data-rate communications compliant with the SpaceWire standard ECSS-E-ST-50-12C Rev.1 (SpaceWire Encoder‐Decoder specification). The SpaceWire protocol defines a bi-directional, full-duplex, serial data communication link, and it is based on LVDS physical layer, resulting in a low-power high-speed link.

The IP Core is available as “simple” CODEC, implementing the full SpaceWire protocol stack and having simple TX/RX FIFO interface for data and access to control and status registers. This is the most flexible version to be integrated in a third-party FPGA/ASIC design. In order to accommodate more complex designs, the IP Core can be extended with Direct Memory Access (DMA) and standard bus interface such as AMBA AXI. This extensions make it easier to use the IP Core within microprocessor-based systems.

The SpaceWire CODEC IP Core has been tested at multiple levels, it is interoperable with other SpaceWire commercial products (e.g., conformance testers), it has been validated in ESA space project, and it has been integrated in space flight hardware for Earth observation missions (e.g., ESA Sentinel-3 mission, ESA Euclid mission) and others (e.g., Iridium NEXT constellation).